1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a data input/output circuit of a three-dimensional (3D) package semiconductor apparatus.
2. Related Art
As electronic devices are pursuing higher performance, higher capacity and smaller size, constituent semiconductor apparatuses have generally become smaller in size while providing enhanced functionality. In order to reduce the size of the semiconductor apparatus, it is required to increase the capacity of a unit package. Therefore, techniques to increase the capacity of the semiconductor apparatus by incorporating a plurality of chips into a single package have been proposed. In addition, researches are actively being conducted on a three-dimensional (3D) package semiconductor apparatus having a through silicon via (TSV) structure, in which a via penetrates and electrically connects a plurality of stacked chips.
A typical 3D package semiconductor apparatus can be designed such that, of the plurality of chips electrically connected via the TSV, one chip is designated as a master chip and the other chip (or chips) are designated as a slave chip, wherein data transmitted from the master chip can be transmitted to the respective slave chips via the TSV and data transmitted from the respective slave chips can be transmitted to the master chip via the TSV.
FIG. 1 is a diagram schematically showing a configuration of a data transmission circuit of the semiconductor apparatus according to the related art. As shown in FIG. 1, the semiconductor apparatus according to the related art can comprise a master chip 10 and a slave chip 20, both of which are electrically connected with each other via a TSV 30. The master chip 10 comprises a master transmission unit 11 and a master receiving unit 12, and correspondingly, the slave chip 20 comprises a slave transmission unit 21 and a slave receiving unit 22. Data inputted to the master chip 10 can be amplified by the master transmission unit 11, and the amplified data can be transmitted to the slave receiving unit 22 via the TSV 30. On the other hand, data stored in the slave chip 20 can be amplified by the slave transmission unit 21, and the amplified data can be transmitted to the master receiving unit 12 via the TSV 30.
FIG. 2 is a diagram showing a configuration of the master transmission unit 11 in FIG. 1 according to the related art. As shown in FIG. 1, the master transmission unit 11 comprises a first NAND gate ND1, a first inverter IV1, a first NOR gate NOR1, and a driver. The first NAND gate ND1 receives a strobe signal IOSTB and master chip data GIO_M. The first NAND gate ND1 outputs a logic low signal if the strobe signal IOSTB is enabled at a logic high level and the master chip data GIO_M is at a logic high level. The first inverter IV1 inverts the strobe signal IOSTB. The first NOR gate NOR1 receives an output signal of the first inverter IV1 and the master chip data GIO_M. Therefore the first NOR gate NOR1 outputs a logic high signal if the strobe signal IOSTB is enabled at a logic high level and the master chip data GIO_M is at a logic low level.
The driver comprises a first p-type metal oxide semiconductor (PMOS) transistor P1 and a first n-type metal oxide semiconductor (NMOS) transistor N1, and generates transmission data GIO_TSV of a logic high level if an output signal of the first NAND gate ND1 is at a logic low level, and generates the transmission data GIO_TSV of a logic low level if an output signal of the first NOR gate NOR1 is at a logic high level.
FIG. 3 is a diagram showing a configuration of the slave receiving unit 22 in FIG. 1 according to the related art. As shown in FIG. 3, the slave receiving unit 22 comprises a second NAND gate ND2, a second inverter IV2 a second NOR gate NOR2, and a driver. If the strobe signal IOSTB is enabled to a logic high level, the slave receiving unit 22 re-amplifies the transmission data GIO_TSV transmitted via the TSV 30 to transmit the amplified data as a slave chip data GIO_S.
Although the semiconductor apparatus shown in FIG. 1 has two stacked chips, three or more chips, in general, are stacked to constitute a single semiconductor apparatus having the TSV structure. Therefore, in general, the TSV 30 transmitting the transmission data GIO_TSV has a very large capacitance. That is, in order to receive the transmission data GIO_TSV, the slave chip has to comprise a receiving unit, e.g., the slave receiving unit 22, and thus, as the number of stacked chips is increased, the number of slave receiving units is also increased, and the capacitance that the master transmission unit 11 faces is also increased. In the state where the capacitance is increased, if a logic level of the transmission data GIO_TSV transmitted via the TSV 30 transitions to its opposite logic level, the transition speed is inevitably decreased. For example, if the master chip data GIO_M changes from a logic low level to a logic high level the transmission data GIO_TSV transits to a logic high level very slowly due to the large capacitance of the TSV 30. Therefore, since the slave receiving unit 22 receiving the transmission data GIO_TSV should wait until the transmission data GIO_TSV transits and perform the sense amplification operation at a relatively late point of time, it is difficult for the slave receiving unit 22 to generate the slave chip data accurately. In addition, since the capacitance of the TSV 30 is very large, the time period necessary to drive the transmission data GIO_TSV is increased, and therefore current consumption is also increased.